The present invention relates to a switching mode power supply, and more particularly to the pulse width modulation (PWM) of the switching mode power supply.
The PWM is a traditional technology used in switching mode power supply to control the output power and achieve the regulation. Most electronic equipments, such as TV, computer, printer, etc., are using the PWM power supply. Based on the restriction of environmental pollution, computers and other equipment manufactures have been striving to meet the power management and energy conservation requirements. The principle of power management is to manage the system to consume power only during its operation, and very little power will be consumed during non-operation (sleep mode). A PWM-control integrated circuit, 3842 family, has been widely used for the power supply in the last decade. It includes 3842, 3843, 3844 and 3845, which build in necessary features to implement a switching power supply. However, it does not include the function of saving energy. With respect to the power supply in a power management application, how to save the power in the no load or light load conditions is a major requirement. Through the frequency modulation in PWM control, this invention reduces power consumption in light load and no load conditions. FIG. 1 shows a circuit schematic of the flyback power supply that includes a 3842 PWM controller 100. A transistor 300 switches a transformer 400. A time constant resistor 210 and capacitor 260 assign the switching frequency for variance of applications. When the transistor 300 is turned off, the leakage inductance of transformer 400 keeps the current, which has been flowing in it constantly for some short time. The part that current continues to flow into the slowly off-switching transistor 300 and the rest of that current flows into a capacitor 275 through a diode 310. A resistor 235 dissipates the energy that is charged in the capacitor 275. The diode 310, resistor 235, and capacitor 275 form a clamp circuit to reduce the leakage inductance spike and avoid the transistor 300 breakdown. At the instance of transistor 300 is switched on, an output rectifier 320 is switched off, and there is an exponentially decaying oscillation or xe2x80x98ringxe2x80x99 will come out. The ring is at a frequency determined by the inherent capacity of the off-switching rectifier 320 and the value of secondary inductance of the transformer 400. The amplitude and duration of the ring are determined by the output current and the reverse recovery times of the rectifier 320. The ring will cause RFI problem and can easily be eliminated by a snubber resistor 240 and a snubber capacitor 280 across the output rectifier 320. The major factors affecting the loss of the power conversion in the light load condition are listed as below:
(1) The switching loss of the transistor 300, PQ can be expressed
(tol/T)(∫0tolVQxc3x97Ip dt),
or
PQ=Fsxc3x97tolxc3x97(∫0tolVQxc3x97Ip dt),
xe2x80x83where T is switching period, Fs is the switching frequency and tol is the duration of overlap of voltage VQ and current Ip. Ip is the primary current of the transformer 400 and VQ is the voltage across the transistor 300.
(2) The switching loss of output rectifier 320 and 330, PD can be expressed
(trr/T)(∫0trrVdxc3x97Id dt),
or
PD=Fsxc3x97trrxc3x97(∫0trrVdxc3x97Id dt),
xe2x80x83where trr is the reverse recovery time of the rectifier. The Vd is the voltage across the rectifier when it is switch-off. Id is limited by the secondary inductance of the transformer 400.
(3) The core loss of transformer 400, PT, it is proportional to flux density Bm, core volume Vv and the switching frequency Fs.
PT=K0xc3x97Bmxc3x97Vvxc3x97Fs,
xe2x80x83where K0 is a constant.
(4) The power loss of snubber, PR is stated as
PR=(xc2xd)xc3x97Cxc3x97Vd2xc3x97Fs,
xe2x80x83where C is the capacitance of the snubber, such as capacitor 280.
(5) The power loss of leakage inductance, PL can be stated by
PL=(xc2xd)xc3x97Ltxc3x97Ip2xc3x97Fs,
xe2x80x83where the Lt is the primary leakage inductance of transformer 400. The resistor 235 dissipates the energy that is produced by the Lt.
We can find that all of the losses are in direct proportion to the switching frequency Fs. However the power supply is designed to operate in a higher frequency to shrink the size, especially the volume of the transformer. To prevent the saturation of the transformer, the voltage-time ratio (Vinxc3x97Ton) has to be managed to limit the flux density Bm of the transformer.
Bm=(Vinxc3x97Ton)/(Npxc3x97Ae),
where Vin is the input voltage of the power supply, Ton is the turn-on time, Np is the primary turn number of the transformer, Ae is the cross of the transformer. The value of (Npxc3x97Ae) represents the size of the transformer. A higher frequency can earn a lower maximum Ton and a smaller transformer.
Take the flyback power supply as an example; the output power Po is equal to (xc2xdT)xc3x97Lpxc3x97Ip2, where Lp is the primary inductance of the transformer 400. Since Ip=(Vin/Lp)xc3x97Ton, it can be seen quantitatively as
Po=(Vin2xc3x97Ton2)/(2xc3x97Lpxc3x97T).
This is seen from that equation, during the light load condition, Ton is short and obviously allows us to widen the T (lower the Fs). The power consumption of the power supply is dramatically reduced in response to the decrease of the switching frequency Fs in the light load condition and no load condition. FIG. 2 shows the circuit schematic of 3842 PWM-controller. The resistor 210 in FIG. 1 is connected from pin VRC to a reference voltage VREF and the capacitor 260 in pin VRC is connected to ground. FIG. 3 displays the waveform for the circuit in FIG. 2. The voltage across capacitor 260 is charged and reaches the trip-point of the comparator 10 (trip-point voltage Vx). The comparator 10 and the NAND gates 17,18 will generate a discharge signal Vp to turn on the transistor 23 that discharges the capacitor 260 via a constant current sink 24. The phenomenal of the discharge is continuous until the voltage of capacitor 260 lower than the low-point voltage Vy, in which a comparator 11 is enabled. The resistor 210, capacitor 260, comparators 10, 11, current sink 24, transistor 23, and NAND gates 17, 18 form an oscillator and generate a constant frequency signal to clock on the flip-flop 20. The comparator 12 resets the flip-flop 20 when the voltage in the pin Vs is higher than the feedback signal VFB. The resistor 230 converts the current information of the transformer 400 to a voltage signal, which is a ramp signal, and the input voltage Vin and the inductance of transformer 400 determine its slope
VR230=R230xc3x97(Vinxc3x97Ton)/Lp.
The voltage in resistor 230, VR230, is inputted to the pin Vs via the filter of a resistor 225 and a capacitor 270. The feedback signal VFB is derived from the output of an error amplifier 14, which is attenuated by resistors RA, RB and the level shift diodes 21, 22. The voltage level of the VFB is dominantly decided by the output power through the control of voltage feedback loop. The discharge time of capacitor 260, which can be demonstrated by Vp when it is high, determines the dead time of the PWM signal 39 that decides the maximum duty cycle of PWM controller 100. The PWM signal will be switched off as long as the voltage of Vs is higher than VFB, thus the maximum VFB is set as 1V to limit the maximum output power. Since a higher power will be output in response to a higher Vin when Vs greater than 1V, a resistor 220 is connected from Vin to pin Vs to compensate the limit for over-power conditions. The compensation added to the pin Vs causes the voltage of VFB to increase automatically through the voltage feedback loop to keep the same Ton and the same output power in the normal operation conditions. For that reason, the voltage of VFB is not only determined by the output power but also affected by a DC bias in pin Vs. According to that observation, the switching frequency Fs can be reduced in response to a low VFB voltage for light load and no load conditions. In addition, the DC bias in pin Vs has to be offset in order to take the reference of VFB. One object of the invention is to add the feature of frequency modulation into the traditional 3842 PWM controllers. Thereafter, without redesigning, most of the power supplies equipped with the 3842 are available for saving energy in light load and no load conditions.
The invention provides a frequency modulation for a PWM controller to reduce the switching frequency in the light load and no load conditions. The frequency modulation is accomplished by moderating the trip-point voltage of the oscillator. Increase in trip-point voltage reduces the switching frequency. The feedback voltage derived from the output of the error amplifier in the voltage feedback loop is taken as an indication. The sense voltage is the voltage of the current sense input of the PWM controller, which represents the information of primary current of the transformer. A sampled voltage is sampled from sense voltage during the PWM signal is turned off. The trip-point voltage is a function of the feedback voltage and the sampled voltage. A threshold voltage is the sum of the sampled voltage and an entry voltage. The entry voltage is a constant that defines a level of light load output power, in which the switching frequency starts to reduce. Once the feedback voltage is lower than the threshold voltage, the trip-point voltage will increase and switching frequency will reduce. When the feedback voltage is higher than the threshold voltage, the trip-point voltage is determined by a primary voltage, which decides the switching frequency in the normal load and high load conditions. The threshold voltage subtracts the feedback voltage is then to be magnified by an amplifier. Via a limiter, the amplified signal is summed with the primary voltage and turned into the trip-point voltage. The limiter clamps the amplified signal between zero and an upper-limit voltage. The sum of the primary voltage and the upper-limit voltage decide the lowest switching frequency of the power supply.
Advantageously, the frequency modulation in the PWM controller can reduce the power consumption of the power supply in light load and no load conditions. And the PWM operations in normal load and high load conditions are as usual and not affected by the frequency modulation.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.